CPU design

• Michal Ondrejka

• GitHub

• november, 2021

The project involves implementing a CPU in VHDL for the programming language Brainf*ck. VHDL, or VHSIC Hardware Description Language, is a programming language used to describe digital circuits and systems. Brainf*ck is a programming language known for its minimalism and difficulty. It consists of only 10 instructions (2nd picture).
The CPU implemented in VHDL is designed to execute Brainf*ck programs, providing a hardware implementation for the language. VHDL code can be synthesized into a real circuit. This approach is more efficient than making physical circuit because any issues can be easily fixed. First thing first, I made a scheme of the CPU (1st picture). This scheme consits of registers, controller, ALU (arithmetic-logic unit), memory and I/O buses. There are three registers CNT (is used to handle nested loops and recutsion), PC (is the address of the instruction) and PTR (points to data in memory). There are are types of architectures based on the location of instructions and data. In Von Neumann architecture data and instructions are in the same memory. In Harvard architecture the data and instructions are in different memories. I chose the Von Neumann since it is mostly used in today's processors. The Questa simulator was used to test the implementation, providing a reliable and efficient platform for simulation and verification. I monitored the signals present in the CPU \ and checked the synchronization with the CLK (clock) signal.