UART

• Michal Ondrejka

• GitHub

• april, 2022

The objective of this project was to design a circuit for receiving data words via an asynchronous serial line (UART).
The design sticks to principles of asynchronous serial communication, with the input data stream consisting of one START bit, 8 data bits, and one STOP bit, transmitted at 9600 baud. The receiving circuit operated at a clock frequency (CLK) 16 times higher than the baud rate. The circuit sampled data bits mid-interval. The UART_RX circuit received bits on the DIN port, deserialized them, and output the resulting 8-bit word on the DOUT port. The validity of the data word was indicated by setting the DOUT_VLD flag to logic level 1 for one clock cycle. Control of the data path was managed using a state diagram (2nd picture). Deliverables included the complete design of the UART_RX circuit, state diagram, and implementation in VHDL.
A functional simulation (3rd picture) demonstrated the circuit's correct operation.
This project provided practical experience in designing a reliable and efficient UART_RX circuit (1st picture), forming a foundation for advanced digital communication systems.